A self-descriptive stack-based PC platform
git clone git://git.luxferre.top/equi.git
Log | Files | Refs | README | LICENSE

DateCommit messageAuthorFiles+-
2022-10-05 14:26updLuxferre2+27-1
2022-09-19 19:37another typofixLuxferre1+1-1
2022-09-19 15:22typofixLuxferre1+1-1
2022-08-21 07:50A better terminal handlingLuxferre1+9-8
2022-08-17 18:30some input upgradesLuxferre2+46-16
2022-08-17 13:22Starting to finalize v0.0.1Luxferre2+1-2
2022-08-16 13:49Some backspace support for a2eLuxferre2+7-2
2022-08-16 13:35Backspace hopefully fixedLuxferre1+10-2
2022-08-16 13:08Figured out some CRLF differencesLuxferre1+19-16
2022-08-16 13:02Streamlined some includesLuxferre1+3-3
2022-08-16 12:55tcc didn't hget hurtLuxferre1+4-22
2022-08-16 08:58some tcc fixesLuxferre1+0-1
2022-08-16 08:51Figured out termiosLuxferre2+38-23
2022-08-14 19:20Attempt to somehow streamline the readmeLuxferre1+0-2
2022-08-14 19:18Attempt to somehow streamline the readmeLuxferre2+66-44
2022-08-14 18:26Apple IIe config figured outLuxferre3+8-19
2022-08-14 15:08Added multitask exampleLuxferre2+34-3
2022-08-14 13:15Implemented some task control portioLuxferre1+28-0
2022-08-14 12:58Updated make target for a2enhLuxferre3+28-16
2022-08-14 06:18Implemented task privilegesLuxferre1+16-10
2022-08-13 20:39Implemented Y instruction for task loadingLuxferre1+3-3
2022-08-13 20:37Implemented Y instruction for task loadingLuxferre1+6-0
2022-08-13 20:19Implemented round-robin task switching mechanismLuxferre1+54-23
2022-08-13 16:05Yet another RAM structure revamp for memory protection and future multitasking - to be reflected in READMELuxferre1+12-11
2022-08-13 15:48Yet another RAM structure revamp for memory protection and future multitasking - to be reflected in READMELuxferre1+137-112
2022-08-13 08:49Correctly implemented write protectionLuxferre2+11-3
2022-08-13 07:58Revamped persistent storage ops to Forth-like 1K-aligned blocksLuxferre2+9-9
2022-08-13 07:24another a2e adjustment and stack size output on interactive bannerLuxferre1+3-3
2022-08-13 05:46memory revamp described, endianness checkedLuxferre2+44-18
2022-08-13 04:40memory layout revampLuxferre1+42-34
2022-08-12 14:34of courseLuxferre1+1-1
2022-08-12 13:14minor readme updateLuxferre1+9-1
2022-08-12 10:07some readme fixesLuxferre1+1-1
2022-08-12 09:57Removed irrelevant example snippet from the README; will be superseded with a proper loader example in the futureLuxferre1+0-10
2022-08-12 09:52implemented silent mode with s command line parameterLuxferre2+16-8
2022-08-12 09:45Fixed VT100-compatible term initLuxferre1+1-1
2022-08-12 09:16fix for TCCLuxferre1+1-0
2022-08-12 09:05Added PERSIST_FILE to make DFLAGSLuxferre1+1-1
2022-08-12 08:58minor persist fixLuxferre2+10-4
2022-08-12 08:50minor persist fixLuxferre2+2-2
2022-08-12 08:46Adapted persfile to 96K and the buffer size to fit AppleIIeLuxferre4+15-9
2022-08-12 08:26Persistent operations implementedLuxferre3+45-9
2022-08-11 20:23terminal and readme improvementsLuxferre2+51-18
2022-08-11 18:05Got rid of unnecessary varLuxferre1+1-1
2022-08-11 17:49Updated min exLuxferre1+2-1
2022-08-11 16:11Implemented minification modeLuxferre3+25-11
2022-08-11 15:38Implemented FizzBuzz example for current spec versionLuxferre2+57-0
2022-08-11 12:39some docs correctionsLuxferre1+4-4
2022-08-11 12:36Port I/O tested; strip unstable again, commented outLuxferre3+42-10
2022-08-11 09:11Some cc65 screen init and welcome prompt fixLuxferre1+7-2
2022-08-11 08:55fixed Q logicLuxferre1+1-1
2022-08-11 08:43Whitespace logic revamped, now Q at the end is mandatory but one can use any whitespace in the programsLuxferre2+22-26
2022-08-11 06:29Implemented G instructionLuxferre2+6-1
2022-08-10 19:14Fixed return instruction and EOF behaviorLuxferre2+4-2
2022-08-10 14:53Fixed return instruction and EOF behaviorLuxferre2+12-8
2022-08-10 13:49Implemented variable-length literals and stringsLuxferre1+20-27
2022-08-09 18:34Got rid of POSIX warnings and re-enabled strip in the makefile for nowLuxferre2+6-5
2022-08-09 17:59Hopefully fixed literals and implemented most instructionsLuxferre2+144-62
2022-08-09 04:47Temporarily commented out stripLuxferre2+54-20
2022-08-08 08:07some instruction progressLuxferre1+122-15
2022-08-08 03:48Some TCC adaptationsLuxferre1+2-1
2022-08-07 19:20some skeleton for further codebaseLuxferre2+240-8
2022-08-06 18:09Made EquiRAM structure the main source of truth about sizingLuxferre1+28-35
2022-08-06 16:02Working config found for apple2enh targetLuxferre1+1-1
2022-08-06 16:01Working config found for apple2enh targetLuxferre2+28-9
2022-08-06 11:01some makefile improvementsLuxferre1+7-3
2022-08-06 10:35Added Makefile to simplify buildsLuxferre4+212-189
2022-08-06 09:14Described how we would build Equi for Apple II and started to debug the processLuxferre4+25-8
2022-08-06 06:34standardizeLuxferre2+39-21
2022-08-06 05:19Fixed readme in terms of real RAM layout and how to compile on ccLuxferre2+34-9
2022-08-05 21:10UpLuxferre1+1-1
2022-08-05 21:09UpLuxferre1+1-1
2022-08-05 21:08UpLuxferre2+259-0