nrj-oisc

commit 4ce53635c853b33af88a245a8ce1312c9f1201bd
parent 24eaaab70de07ebb79650892c11534563ff350f9
Author: Luxferre <lux@ferre>
Date:   Sat,  3 Sep 2022 07:58:16 +0300

Git rid of some hardcoding

Diffstat:
M
nrjasm.py
 | 
10
+++++-----

1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/nrjasm.py b/nrjasm.py
@@ -171,18 +171,18 @@ def start_assembly(srcfname, dstfname): # main assembly method
         elif line[0] == NRJDIR_SET: # handle .set
             addr = int(line[1], 16)
             val = line[2]
-            if val == 'HLT':
+            if val == NRJDIR_HLT:
                 targetmem[addr] = ltoffset
-            elif val != 'NXT':
+            elif val != NRJDIR_NXT:
                 targetmem[addr] = int(val, 16)
         else: # 3-value vector where HLT or NXT can be encountered
             # save current instruction in the lookup table
             targetmem[ltoffset + ltpos] = codepos
             ltpos += 1
             for v in line:
-                if v == 'HLT':
+                if v == NRJDIR_HLT:
                     targetmem[codepos] = ltoffset
-                elif v == 'NXT':
+                elif v == NRJDIR_NXT:
                     targetmem[codepos] = ltoffset + ltpos
                 else:
                     targetmem[codepos] = int(v, 16)
@@ -196,7 +196,7 @@ def start_assembly(srcfname, dstfname): # main assembly method
         elif line[0] == NRJDIR_SET: # handle .set
             addr = int(line[1], 16)
             val = line[2]
-            if val == 'NXT':
+            if val == NRJDIR_NXT:
                 val = targetmem[ltoffset + ltpos]
                 targetmem[addr] = val
         else: # 3-value vector where HLT or NXT can be encountered